Cisco Senior ASIC Backend Engineer in San Jose, California
Senior ASIC Backend Engineer
Location: San Jose, California, US
Area of Interest Engineer - Hardware
Job Type Professional
Technology Interest Cloud and Data Center, Networking
Job Id 1226963
What You'll Do
Looking for a talented and motivated ASIC backend leader specializing in timing – timing analysis and closure, helping to construct and modify flows, working with designers for timing changes. If you’re looking to join a top-notch ASIC development team that leads the market with innovative silicon for datacenter (Switching, Storage, VIC), then look no further.
You will collaborate closely with the architecture, hardware, and software teams to design, develop, verify, and validate Data Center networking ASICs working across product generations, networking technologies, and protocols. There are only a handful of teams in the world that implement and deliver successful ASICs at this performance and scale, and we take pride in the impact of our work. Every time you access the internet, chances are, your data is going through one of our ASICs.
Architecting timing methodology for large switching ASICs
Working with design teams to develop, understand and debug constraints, facilitate logic changes to improve timing
Working with Physical Design and Logic Design teams, highlighting issues and best practices
Help create timing ECO’s for project tapeout
Create/maintain timing scripts and methodologies for analysis and runs
Create documentation and help with guidelines/specs
Deep analysis of timing paths to identify key issues
Implement timing infrastructure
Who You'll Work With
Come join us and take part in shaping Cisco’s revolutionary solutions for datacenters by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!
Who You Are
Architected and implemented timing sign-off methodology for large switching ASICs
Expertise with STA on large, complex designs and Multi-Scenario Timing Closure
Familiar with all aspects of timing of large high-performance SoC designs in sub- micron technologies
Timing Margin Fundamentals from synthesis to signoff
Needs to be proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross- talk, and OCV effects, among others
Familiar with circuit modeling, including SPICE models and worst-case corner selection.
Programming with Perl, TCL
Timing Flow using industry standard tools.
Familiarity with ECO techniques and implementation
Familiarity with power recovery techniques using STA tools
Good communicator who can accurately describe issues and follow them through to completion
Bachelor’s or Master’s degree in Electrical Engineering
The ideal candidate will have 10+ years of hands on experience in STA with leadership role in architecting timing methodology for large switch ASICs
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