Cisco Technical Leader Asic Physical Design SC in San Jose, California
Technical Leader Asic Physical Design SC
Location: San Jose, California, US
Area of Interest Engineer - Hardware
Job Type Professional
Technology Interest Networking
Job Id 1225971
WHO YOU'LL WORK WITH:
Our creative and talented team as Physical Design Lead in San Jose, CA. As a member of this team you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place&route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
WHAT YOU WILL DO:
Responsible for RTL2GDS implementation of multi-hierarchy designs in 7nm TSMC technology
Perform partition, pin assignment and assemble design process tasks
Participate in defining Physical and Timing Sign-Off conditions
Work closely with RTL design team to understand the design architecture and drive design physical planning aspects
As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work
Resolve design and flow issues related to physical design, identify potential solutions and drive execution
WHO YOU ARE:
You are a HW engineer with 10+ years of related work experience with a broad mix of technologies including:
All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Hierarchical design implementation approach, Timing closure, physical convergence.
Power Integrity Analysis
Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7nm technologies.
Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies
You should also have hands on experience with the following Tool sets
Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
Synthesis Tools: Synopsys DC/DCG
Formal Verification : Synopsys Formality and Cadence LEC
Static Timing verification: Primetime-DMSA
Power Integrity : Apache Redhawk
Physical Design Verification Synopsys ICV, Mentor Calibre
Scripting: TCL, Perl is required; Python is a plus
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
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